메뉴 건너뛰기




Volumn 27, Issue PART 2, 2002, Pages 129-162

Efficient algorithms for approximate time separation of events

Author keywords

Approximate algorithms; Asynchronous systems; Bounded delay timing analysis; Convex approximation; Time separation of events; Timing analysis and verification

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTER SIMULATION; CONSTRAINT THEORY; POLYNOMIAL APPROXIMATION; THEOREM PROVING;

EID: 0036544624     PISSN: 02562499     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF02717181     Document Type: Article
Times cited : (5)

References (45)
  • 1
    • 51549096502 scopus 로고
    • Logics and models of real-time: A survey
    • Real time: Theory in practice. (eds) J W de Bakker, K Huizing, W P de Roever, G Rosenberg (Berlin: Springer-Verlag)
    • Alur R, Henzinger T A 1992 Logics and models of real-time: A survey. In Real time: Theory in practice. Lecture Notes in Computer Science #600 (eds) J W de Bakker, K Huizing, W P de Roever, G Rosenberg (Berlin: Springer-Verlag) pp. 74-106
    • (1992) Lecture Notes in Computer Science , vol.600 , pp. 74-106
    • Alur, R.1    Henzinger, T.A.2
  • 6
    • 0030679983 scopus 로고    scopus 로고
    • Symbolic timing verification of timing diagrams using Presburger formulas
    • Los Alamitos, CA: IEEE Comput. Soc. Press
    • Amon T, Borriello G, Hu D, Liu J 1997 Symbolic timing verification of timing diagrams using Presburger formulas. In Proceedings of the ACM/IEEE Design Automation Conference (Los Alamitos, CA: IEEE Comput. Soc. Press) pp 226-231
    • (1997) Proceedings of the ACM/IEEE Design Automation Conference , pp. 226-231
    • Amon, T.1    Borriello, G.2    Hu, D.3    Liu, J.4
  • 9
    • 84987028346 scopus 로고
    • Consistency and satisfiability of waveform timing specifications
    • Brzozowski J A, Gahlinger T, Mavaddat F 1991 Consistency and satisfiability of waveform timing specifications. Networks 21: 91-107
    • (1991) Networks , vol.21 , pp. 91-107
    • Brzozowski, J.A.1    Gahlinger, T.2    Mavaddat, F.3
  • 10
  • 15
    • 0031629742 scopus 로고    scopus 로고
    • Practical timing analysis of asynchronous circuits using time separations of events
    • Los Alamitos, CA: IEEE Comput. Soc. Press
    • Chakraborty S, Yun K Y, Dill D L 1998 Practical timing analysis of asynchronous circuits using time separations of events. In Proceedings of the IEEE Custom Integrated Circuits Conference (Los Alamitos, CA: IEEE Comput. Soc. Press) pp 455-458
    • (1998) Proceedings of the IEEE Custom Integrated Circuits Conference , pp. 455-458
    • Chakraborty, S.1    Yun, K.Y.2    Dill, D.L.3
  • 16
    • 0032631994 scopus 로고    scopus 로고
    • Timing analysis of asynchronous systems using time separation of events
    • Chakraborty S, Yun K Y, Dill D E 1999 Timing analysis of asynchronous systems using time separation of events. IEEE Trans. Comput. Aided Design 18: 1061-1076
    • (1999) IEEE Trans. Comput. Aided Design , vol.18 , pp. 1061-1076
    • Chakraborty, S.1    Yun, K.Y.2    Dill, D.E.3
  • 17
    • 0029216608 scopus 로고
    • Interval scheduling: Fine-grained code scheduling for embedded systems
    • Los Alamitos, CA: IEEE Comput. Soc. Press
    • Chou P, Borriello G 1995 Interval scheduling: Fine-grained code scheduling for embedded systems. In Proceeding of the ACM/IEEE Design Automation Conference (Los Alamitos, CA: IEEE Comput. Soc. Press) pp. 462-467
    • (1995) Proceeding of the ACM/IEEE Design Automation Conference , pp. 462-467
    • Chou, P.1    Borriello, G.2
  • 20
    • 0031076573 scopus 로고    scopus 로고
    • Solving linear, min and max constraint systems using CLP based on relational arithmetic
    • Girodias P, Cerny E, Older W J 1997 Solving linear, min and max constraint systems using CLP based on relational arithmetic. Theor. Comput. Sci. 173: 253-281
    • (1997) Theor. Comput. Sci. , vol.173 , pp. 253-281
    • Girodias, P.1    Cerny, E.2    Older, W.J.3
  • 21
    • 4243678276 scopus 로고
    • Timing analysis of digital circuits and the theory of min-max functions
    • Hewlett-Packard Laboratory, Palo Alto, CA
    • Gunawardena J 1994 Timing analysis of digital circuits and the theory of min-max functions. Tech. Rep. HPL-94-39, Hewlett-Packard Laboratory, Palo Alto, CA
    • (1994) Tech. Rep. HPL-94-39
    • Gunawardena, J.1
  • 24
    • 4244197012 scopus 로고
    • An algorithm for exact bounds on time separation of events in concurrent systems
    • Dept. of Computer Sci. Eng., Univ. of Washington, Seattle, WA
    • Hulgaard H, Burns S M, Amon T, Borriello G 1994 An algorithm for exact bounds on time separation of events in concurrent systems. Tech. Report, No. UW-CSE-94-02-02, Dept. of Computer Sci. Eng., Univ. of Washington, Seattle, WA
    • (1994) Tech. Report, No. UW-CSE-94-02-02
    • Hulgaard, H.1    Burns, S.M.2    Amon, T.3    Borriello, G.4
  • 25
    • 2342418657 scopus 로고
    • An algorithm for exact bounds on time separation of events in concurrent systems
    • Hulgaard H, Burns S M, Amon T, Bordello G 1995 An algorithm for exact bounds on time separation of events in concurrent systems. IEEE Trans. Comput. 44: 1306-1317
    • (1995) IEEE Trans. Comput. , vol.44 , pp. 1306-1317
    • Hulgaard, H.1    Burns, S.M.2    Amon, T.3    Bordello, G.4
  • 27
    • 0028370467 scopus 로고
    • Linear programming for optimum hazard elimination in asynchronous circuits
    • Lavagno L, Sangiovanni-Vincentelli A L 1994 Linear programming for optimum hazard elimination in asynchronous circuits. J. VLSI Signal Process. 7: 137-60
    • (1994) J. VLSI Signal Process. , vol.7 , pp. 137-160
    • Lavagno, L.1    Sangiovanni-Vincentelli, A.L.2
  • 29
    • 0032047615 scopus 로고    scopus 로고
    • On deducing timing constraints in the verification of interfaces
    • Mavaddat F, Gahlinger T 1998 On deducing timing constraints in the verification of interfaces. Formal Methods Syst. Design 12: 223-239
    • (1998) Formal Methods Syst. Design , vol.12 , pp. 223-239
    • Mavaddat, F.1    Gahlinger, T.2
  • 31
    • 0009997968 scopus 로고    scopus 로고
    • Difference decision diagrams
    • Department of Information Technology, Technical University of Denmark, Lyngby
    • Mller J, Lichtenberg J, Andersen H R, Hulgaard H 1999 Difference decision diagrams. Tech. Rep. IT-TR-1999-023, Department of Information Technology, Technical University of Denmark, Lyngby
    • (1999) Tech. Rep. IT-TR-1999-023
    • Mller, J.1    Lichtenberg, J.2    Andersen, H.R.3    Hulgaard, H.4
  • 37
    • 0010002438 scopus 로고
    • Specification and analysis of timing constraints in signal transition graphs
    • Los Alamitos, CA: IEEE Comput. Soc. Press
    • Vanbekbergen P, Goossens G, De Man H 1992 Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference (Los Alamitos, CA: IEEE Comput. Soc. Press) pp 302-306
    • (1992) Proceedings of the European Design Automation Conference , pp. 302-306
    • Vanbekbergen, P.1    Goossens, G.2    De Man, H.3
  • 39
    • 0028571332 scopus 로고
    • Interface timing verification with application to synthesis
    • Los Alamitos, CA: IEEE Comput. Soc. Press
    • Walkup E A, Borriello G 1994 Interface timing verification with application to synthesis. In Proceedings of the ACM/IEEE Design Automation Conference (Los Alamitos, CA: IEEE Comput. Soc. Press) pp 106-112
    • (1994) Proceedings of the ACM/IEEE Design Automation Conference , pp. 106-112
    • Walkup, E.A.1    Borriello, G.2
  • 40
    • 0028369772 scopus 로고
    • Performance of iterative computation in self-timed rings
    • Williams T E 1994 Performance of iterative computation in self-timed rings. J. VLSI Signal Process. 7: 17-31
    • (1994) J. VLSI Signal Process. , vol.7 , pp. 17-31
    • Williams, T.E.1
  • 45
    • 0032303142 scopus 로고    scopus 로고
    • The design and verification of a high-performance low-control-overhead asynchronous differential equation solver
    • Yun K Y, Beerel P A, Vakilotojar V, Dooply A E, Arceo J 1998 The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. IEEE Trans. VLSI Syst. 6: 643-655
    • (1998) IEEE Trans. VLSI Syst. , vol.6 , pp. 643-655
    • Yun, K.Y.1    Beerel, P.A.2    Vakilotojar, V.3    Dooply, A.E.4    Arceo, J.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.