Verification of out-of-order processor designs using model checking and a light-weight completion function

Formal Methods in System Design

Volumn 20, Issue 2, 2002, Pages 159-186

  Berezin, Sergey ^a   Clarke, Edmund ^a   Biere, Armin ^b   Zhu, Yunshan ^c  

^a Carnegie Mellon University ^*  (United States)

^b ETH ZURICH   (Switzerland)

^c SYNOPSYS INC   (United States)

Author keywords

Completion function; Formal verification; Model checking; Reference file; Theorem proving; Tomasulo's algorithm

Indexed keywords

FORMAL VERIFICATION; LIGHT WEIGHT COMPLETION FUNCTION; MODEL CHECKING; REFERENCE FILE REPRESENTATION; SUPERSCALAR PROCESSOR; TOMASULO ALGORITHM;

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING; THEOREM PROVING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

DESIGN FOR TESTABILITY;

EID: 0036500942     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1014170513439     Document Type: Article

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