Retiming and clock scheduling for digital circuit optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 2, 2002, Pages 184-203

  Liu, Xun ^a,b   Papaefthymiou, Marios C ^a,b   Friedman, Eby G ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c University of Rochester   (United States)

Author keywords

Delay tolerance; Digital circuits; Optimization delay variations; Retiming; Scheduling; Timing

Indexed keywords

CLOCK SCHEDULING; MIXED-INTEGER LINEAR PROGRAMMING; RETIMING;

ELECTRIC NETWORK SYNTHESIS; HEURISTIC METHODS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; OPTIMIZATION; THEOREM PROVING; TIMING CIRCUITS;

DIGITAL INTEGRATED CIRCUITS;

EID: 0036474593     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.980258     Document Type: Article

References (24)

1. Cycle time and slack optimization for VLSI-chips
2. Resynthesis and retiming for optimum partial scan
3. Retiming and clock skew for synchronous systems
4. A graph-theoretic approach to clock skew optimization
5. Retiming sequential circuits to enhance testability
6. Clock skew optimization
7. Optimizing two-phase, level-clocked circuitry
8. DELAY: An efficient tool for retiming with realistic delay modeling
9. Retiming synchronous circuitry
10. Maximizing performance by retiming and clock skew scheduling
11. Optimal clock skew scheduling tolerant to process variations
12. Optimal retiming of multi-phase, level-clocked circuits
13. The practical application of retiming to the design of high-performance system
14. Retiming by combination of relocation and clock delay adjustment
15. Retiming sequential circuits for low power
16. Optimal clock skew scheduling tolerant to process variations
17. TIM: A timing package for two-phase, level-clocked circuitry
18. Retiming of circuits with single phase level-sensitive latches
19. Incorporating interconnect, register, and clock distribution delays into the retiming process
20. Understanding retiming through maximum average-delay cycles
21. Retiming with non-zero clock skew, variable register and interconnect delay
22. A fresh look at retiming via clock skew optimization