Retiming and clock skew for synchronous systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1994, Pages 283-286

  Chao, Liang Fang ^a   Sha, Edwin Hsing Mean ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; FLIP FLOP CIRCUITS; OPTIMIZATION; SCHEDULING; SIGNAL PROCESSING;

CLOCKING SIGNAL; FRACTIONAL TIMING MODEL; SYNCHRONOUS CIRCUITRY; UNIT TIME CIRCUIT;

TIMING CIRCUITS;

EID: 0028582437     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)