Retiming sequential circuits to enhance testability

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1994, Pages 28-33

  Dey, Sujit ^a   Chakradhar, Srimat T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

RETIMING FOR REGISTER MINIMIZATION; RETIMING OF TESTABILITY;

SEQUENTIAL CIRCUITS;

EID: 0028741360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)