Formal verification of PowerPCTM arrays using symbolic trajectory evaluation

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 649-654

  Pandey, Manish ^a   Raimi, Richard ^a   Beatty, Derek L ^a   Bryant, Randal E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; BUFFER STORAGE; COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; DECISION TABLES; FORMAL LANGUAGES; LOGIC DESIGN; MICROPROCESSOR CHIPS; SHIFT REGISTERS; STATE ASSIGNMENT; STORAGE ALLOCATION (COMPUTER);

MEMORY ARRAYS; STATE HOLDING ELEMENTS; SYMBOLIC TRAJECTORY EVALUATION (STE);

SEMICONDUCTOR STORAGE;

EID: 0029720912     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)