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Volumn 17, Issue 4, 2000, Pages 61-76

Validating PowerPC microprocessor custom memories

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER TESTING; DATA STORAGE EQUIPMENT;

EID: 0343371799     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.895007     Document Type: Article
Times cited : (24)

References (18)
  • 1
    • 0030398539 scopus 로고    scopus 로고
    • PowerPC Array Verification Methodology using Formal Techniques
    • Washington, D.C.
    • N. Ganguly, M. Abadir, and M. Pandey, "PowerPC Array Verification Methodology using Formal Techniques," In'l. Test Conf., Washington, D.C., 1996, pp. 857-864
    • (1996) In'l. Test Conf. , pp. 857-864
    • Ganguly, N.1    Abadir, M.2    Pandey, M.3
  • 2
    • 0029720912 scopus 로고    scopus 로고
    • Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation
    • June
    • M. Pandey et al., "Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation," Proc. 33rd ACM/IEEE Design Automation Conf., June 1996, pp. 649-654.
    • (1996) Proc. 33rd ACM/IEEE Design Automation Conf. , pp. 649-654
    • Pandey, M.1
  • 3
    • 0029292183 scopus 로고
    • Comparing Layouts with HDL Models: A Formal Verification Technique
    • Apr.
    • T. Kam and P.A. Subrahmanyam, "Comparing Layouts with HDL Models: A Formal Verification Technique," IEEE Trans. on Computer-Aided Design, Apr. 1995, pp. 503-509.
    • (1995) IEEE Trans. on Computer-Aided Design , pp. 503-509
    • Kam, T.1    Subrahmanyam, P.A.2
  • 5
    • 0022706656 scopus 로고
    • Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications
    • E.M. Clarke, E.A. Emerson, and A.P. Sistla, "Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications," ACM Trans. on Programming Languages and Systems Vol. 8, No. 2, 1986 pp. 244-263.
    • (1986) ACM Trans. on Programming Languages and Systems , vol.8 , Issue.2 , pp. 244-263
    • Clarke, E.M.1    Emerson, E.A.2    Sistla, A.P.3
  • 6
  • 9
    • 0004491861 scopus 로고
    • Formal Verification of Digital Circuits Using Symbolic Ternary System Models
    • E.M. Clarke, and R.P. Kurshan, eds., American Mathematical Society
    • R.E. Bryant and C.-J.H. Seger "Formal Verification of Digital Circuits Using Symbolic Ternary System Models," Computer-Aided Verification 1990, E.M. Clarke, and R.P. Kurshan, eds., American Mathematical Society, 1991, pp. 121-146.
    • (1991) Computer-Aided Verification 1990 , pp. 121-146
    • Bryant, R.E.1    Seger, C.-J.H.2
  • 11
    • 0018307925 scopus 로고
    • The Application of Program Verification Techniques to Hardware Verification
    • J.A. Darringer "The Application of Program Verification Techniques to Hardware Verification," Proc. 16th ACM IEEE Design Automation Conf., 1979, pp. 375-381.
    • (1979) Proc. 16th ACM IEEE Design Automation Conf. , pp. 375-381
    • Darringer, J.A.1
  • 12
    • 0022769976 scopus 로고
    • Graph-Based Algorithms for Boolean Function Manipulation
    • August
    • R.E. Bryant "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, August 1986, pp. 677-691.
    • (1986) IEEE Trans. Computers , vol.C-35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 13
    • 0003464679 scopus 로고
    • Voss - A formal hardware verification system: User's guide
    • Dept. of Computer Science, University of British Columbia
    • C.-J.H. Seger "Voss - a formal hardware verification system: user's guide," Technical Report 93-45, Dept. of Computer Science, University of British Columbia, 1993.
    • (1993) Technical Report 93-45
    • Seger, C.-J.H.1
  • 14
    • 0001510331 scopus 로고
    • Formal Verification by Symbolic Evaluation of Partially Ordered Trajectories
    • C.-J.H. Seger and R.E. Bryant, "Formal Verification by Symbolic Evaluation of Partially Ordered Trajectories," Formal Methods in System Design, vol. 6, 1995, pp. 147-189.
    • (1995) Formal Methods in System Design , vol.6 , pp. 147-189
    • Seger, C.-J.H.1    Bryant, R.E.2
  • 16
    • 0033734074 scopus 로고    scopus 로고
    • Validation of PowerPC Custom Memories Using Symbolic Simulation
    • Apr.
    • N. Krishnamurthy et al., "Validation of PowerPC Custom Memories Using Symbolic Simulation," Proc. 18th IEEE VLSI Test Symp., Apr. 2000, pp. 9-14.
    • (2000) Proc. 18th IEEE VLSI Test Symp. , pp. 9-14
    • Krishnamurthy, N.1
  • 17
    • 0031641691 scopus 로고    scopus 로고
    • Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation
    • L.-C. Wang, M. Abadir, and N. Krishnamurthy, "Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation," Proc. 35th Design Automation Conf., 1998.
    • (1998) Proc. 35th Design Automation Conf.
    • Wang, L.-C.1    Abadir, M.2    Krishnamurthy, N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.