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Volumn 15, Issue 1, 1999, Pages 191-205

Experience in validation of PowerPCTM microprocessor embedded arrays

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; MICROPROCESSOR CHIPS;

EID: 0033348669     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008352805631     Document Type: Article
Times cited : (6)

References (15)
  • 1
    • 0030398539 scopus 로고    scopus 로고
    • PowerPC Array Verification Methodology Using Formal Verification Techniques
    • Washington, DC
    • N. Ganguly, M.S. Abadir, and M. Pandey, "PowerPC Array Verification Methodology Using Formal Verification Techniques," Proc. International Test Conference, Washington, DC, 1996, pp. 857-864.
    • (1996) Proc. International Test Conference , pp. 857-864
    • Ganguly, N.1    Abadir, M.S.2    Pandey, M.3
  • 4
    • 0342644647 scopus 로고    scopus 로고
    • Automatic Generation of Assertions for Formal Verification of PowerPC™ Microprocessor Arrays
    • Li-C. Wang and M.S. Abadir, "Automatic Generation of Assertions for Formal Verification of PowerPC™ Microprocessor Arrays," Proc. Design Automation Conference, 1998.
    • (1998) Proc. Design Automation Conference
    • Wang, L.-C.1    Abadir, M.S.2
  • 5
    • 0032182502 scopus 로고    scopus 로고
    • Test Generation Based on High-Level Assertion Specification for PowerPC™ Microprocessor Embedded Arrays
    • Li-C. Wang and M.S. Abadir, "Test Generation Based on High-Level Assertion Specification for PowerPC™ Microprocessor Embedded Arrays," Journal of Electronic Testing, No. 13, pp. 121-135, 1998.
    • (1998) Journal of Electronic Testing , Issue.13 , pp. 121-135
    • Wang, L.-C.1    Abadir, M.S.2
  • 6
    • 0032316632 scopus 로고    scopus 로고
    • On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC™ Microprocessor Arrays
    • Li-C. Wang, M.S. Abadir, and J. Zeng, "On Logic and Transistor Level Design Error Detection of Various Validation Approaches For PowerPC™ Microprocessor Arrays," Proc. VLSI Test Symposium, 1998.
    • (1998) Proc. VLSI Test Symposium
    • Wang, L.-C.1    Abadir, M.S.2    Zeng, J.3
  • 10
    • 0001510331 scopus 로고
    • Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
    • C.J.H. Seger and R.E. Bryant, "Formal Verification By Symbolic Evaluation of Partially-Ordered Trajectories," Formal Methods in System Design, Vol. 6, pp. 147-189, 1995.
    • (1995) Formal Methods in System Design , vol.6 , pp. 147-189
    • Seger, C.J.H.1    Bryant, R.E.2
  • 12
    • 0026913667 scopus 로고
    • Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams
    • Sept.
    • R.E. Bryant, "Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams," ACM Computing Surveys, Vol. 24, No. 3, Sept. 1992.
    • (1992) ACM Computing Surveys , vol.24 , Issue.3
    • Bryant, R.E.1
  • 13
    • 0003464679 scopus 로고
    • Voss - A Formal Hardware Verification System: User's Guide
    • Department of Computer Science, University of British Columbia
    • C.J.H. Seger, "Voss - A Formal Hardware Verification System: User's Guide," Technical Report 93-45, Department of Computer Science, University of British Columbia, 1993.
    • (1993) Technical Report 93-45
    • Seger, C.J.H.1
  • 14
    • 0021377624 scopus 로고
    • A Switch-Level Model and Simulator for MOS Digital Systems
    • Feb.
    • R.E. Bryant, "A Switch-Level Model and Simulator for MOS Digital Systems," IEEE Transactions on Computers, Vol. C-33, No. 2, pp. 160-177, Feb. 1984.
    • (1984) IEEE Transactions on Computers , vol.C-33 , Issue.2 , pp. 160-177
    • Bryant, R.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.