Analog macromodeling of capacitive coupling faults in digital circuit interconnects

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 375-383

  Sathe, Aditya D ^a   Bushnell, Michael L ^b   Agrawal, Vishwani D ^c  

^a INTEL CORPORATION   (United States)

^b RUTGERS UNIVERSITY   (United States)

^c AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; CROSSTALK; DIGITAL INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; LOGIC GATES; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

ANALOG MACROMODELING; CROSSTALK CANDIDATE REDUCTION ALGORITHM; DIGITAL CIRCUIT INTERCONNECTS;

INTEGRATED CIRCUIT TESTING;

EID: 0036443122     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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