Combinational test generation for acyclic sequential circuits using a balanced ATPG model

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 143-148

  Yong Chang Kim, ^a   Agrawal, V D ^a   Saluja, K K ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; DESIGN FOR TESTABILITY; FAULT TREE ANALYSIS; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; VECTORS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); COMBINATIONAL TEST GENERATION; RETIMING-LIKE TRANSFORMATIONS;

SEQUENTIAL CIRCUITS;

EID: 0034998851     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)