Sequential circuits with combinational test generation complexity under single-fault assumption

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 1, 2002, Pages 55-62

  Inoue, Michiko ^a   Gizdarski, Emil ^a,b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b UNIVERSITY OF RUSE   (Bulgaria)

Author keywords

Balanced structure; Combinational circuit; Internally balanced structure; Sequential circuit; Test generation

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; SEQUENTIAL CIRCUITS;

INTERNALLY BALANCED STRUCTURES; SEPARABLE PRIMARY INPUTS;

INTEGRATED CIRCUIT TESTING;

EID: 0036471752     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1013728006805     Document Type: Article

References (10)

1. Sequential circuits with combinational test generation complexity
2. Single-fault fault-collapsing analysis in sequential logic circuits
3. Fanout fault analysis for digital logic circuits
4. A new class of sequential circuits with combinational test generation complexity
5. Partial scan design of register-transfer level circuits
6. The BALLAST methodology for structured partial scan design
7. An optimal time expansion model based on combinational ATPG for RT level circuits
8. Multiple fault detection in two-level multi-output circuits