Sequential circuits with combinational test generation complexity

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 111-117

  Balakrishnan, Arun ^a   Chakradhar, Srimat T ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTATIONAL COMPLEXITY; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SET THEORY; SHIFT REGISTERS; VLSI CIRCUITS;

BALANCED STRUCTURES; BENCHMARK CIRCUITS; COMBINATIONAL TEST GENERATORS; DESIGN FOR TESTABILITY TECHNIQUE; PARTIAL SCAN;

SEQUENTIAL CIRCUITS;

EID: 0029699879     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)