Low-power circuit advantages of the scaled accumulation FET

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Murali, Raghunath ^a   Wang, Lihui ^a   Austin, Blanca L ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC INVERTERS; MATHEMATICAL MODELS; NANOTECHNOLOGY; POWER ELECTRONICS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

BURIED CHANNEL ACCUMULATION; SCALED ACCUMULATION FIELD EFFECT TRANSISTORS; ULTRA LOW-POWER APPLICATIONS;

FIELD EFFECT TRANSISTORS;

EID: 0036287558     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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11. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors