Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1999, Pages 109-110

  Tanaka, T ^a   Momiyama, Y ^a   Goto, K ^a   Sambonsugi, Y ^a   Deura, M ^a   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); LSI CIRCUITS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR QUANTUM WELLS; THRESHOLD VOLTAGE;

BURRIED CHANNEL; SUPPRESSING SHORT CHANNEL EFFECTS; TILTED WELL IMPLANTATION;

MOSFET DEVICES;

EID: 0033280029     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)