Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 25, Issue 1, 2002, Pages 42-50

  Lau, John H ^a,b  

^a IEEE   (United States)

^b AGILENT TECHNOLOGIES   (United States)

Author keywords

Cost; Flip chip; Solder joint reliability; Underfill; Wafer bumping; WLCSP

Indexed keywords

WAFER LEVEL CHIP SCALE PACKAGE (WLCSP);

COSTS; DEFORMATION; FLIP CHIP DEVICES; HYSTERESIS; PRINTED CIRCUIT BOARDS; RELIABILITY; SHEAR STRESS; SOLDERED JOINTS; STRAIN;

CHIP SCALE PACKAGES;

EID: 0036287347     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2002.1000482     Document Type: Article

References (23)

1. Wafer level chip scale packaging (WL-CSP): An overview
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5. One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications
6. 3)
7. Wafer level CSP using low cost electroless redistribution layer
8. Recent advances on a wafer-level flip chip packaging process
9. Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies
10. Nonlinear fracture mechanics analysis of wafer-level chip scale package solder joints with cracks
11. A novel and reliable wafer-level chip scale package (WLCSP)
12. Fabrication of wafer level chip scale packaging for optoelectronic devices
13. Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis
14. Cost analysis: Solder bumped flip chip versus wire bonding
15. Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints