VLSI floorplanning with boundary constraints based on corner block list

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 509-514

  Ma, Yuchun ^a   Dong, Sheqin ^a   Hong, Xianlong ^a   Cai, Yici ^a   Cheng, Chung Kuan ^b   Gu, Jun ^c  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Circuit simulation; Clustering algorithms; Computer science; Costs; Design engineering; Integrated circuit interconnections; Large scale integration; Simulated annealing; Topology; Very large scale integration

Indexed keywords

BENCHMARKING; CIRCUIT SIMULATION; CLUSTERING ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SCIENCE; COST ENGINEERING; COSTS; DESIGN; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT INTERCONNECTS; LSI CIRCUITS; SIMULATED ANNEALING; TOPOLOGY; VLSI CIRCUITS;

BOUNDARY CONSTRAINTS; CORNER BLOCK LISTS; DESIGN ENGINEERING; FLOOR-PLANNING; INTEGRATED CIRCUIT INTERCONNECTIONS; LINEAR TIME; VLSI DESIGN; VLSI FLOORPLANNING;

INTEGRATED CIRCUIT DESIGN;

EID: 84949752382     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913359     Document Type: Conference Paper

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