Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 342-343+463

  Van Heijningen, M ^a   Badaroglu, M ^a   Donnay, S ^a   De Man, H ^a   Gielen, G ^a   Engels, M ^a   Bolsens, I ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL CIRCUITS; DIGITAL SIGNAL PROCESSING; MATHEMATICAL MODELS;

COMPLEX DIGITAL SYSTEMS;

NOISE GENERATORS;

EID: 0035058164     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Reduced substrate noise digital design for improving embedded analog performance
2. Analysis and experimental verification of digital substrate noise generation for epi-type substrates
3. High-performance flexible all-digital quadrature up and down converter chip
4. High-level simulation of substrate noise generation including power supply noise coupling