Comparison of mask writing tools and mask simulations for 0.16 μm devices

10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, ASMC 1999

Volumn , Issue , 1999, Pages 372-377

  Balasinski, A ^a   Coburn, D ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MANUFACTURE; PHOTORESISTS; SEMICONDUCTOR DEVICE MANUFACTURE; STATIC RANDOM ACCESS STORAGE;

CONTACT HOLES; DEEP SUBMICRON DEVICE; DESIGN FEATURES; LINE END SHORTENINGS; MASK CORNER ROUNDING; MASK SIMULATION; OPTICAL PROXIMITY CORRECTIONS; PATTERN REPRODUCTION;

PHOTOLITHOGRAPHY;

EID: 84994403062     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.1999.798268     Document Type: Conference Paper

References (3)

1. A. Balasinski and K. Kim, Simulation of Photolithographic Mask for Image Optimization in Static Memory Fabrication, The 195' Mtg. of the Electrochem. Soc. , May 2-6, 1999, Abs. 222.
2. A. Balasinski and K. Kim, Improving the Accuracy of Photolithography Image Prediction by Reticle Simulation, patent pending.
3. M. Ishida, T. Kawakami, A. Tsuji, N. Kawamoto, M. Motoyoshi, and N. Ouchi, A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns Scalable beyond 0. 18 pm generation and Desirable for Ultra High Speed Operation, Proc. IEDM 1998, p. 201.