Optimizing the cost of design rule modifications for subsequent generations of semiconductor technology

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn 2000-January, Issue , 2000, Pages 256-262

  Balasinski, A ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

Cost function; Design optimization; Geometry; Manufacturing processes; Process design; Product development; Scalability; Semiconductor device manufacture; Silicon; Spatial databases

Indexed keywords

COST FUNCTIONS; COSTS; DESIGN; GEOMETRY; MANUFACTURE; PROCESS DESIGN; PRODUCT DESIGN; PRODUCT DEVELOPMENT; SCALABILITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES; SILICON;

AGGRESSIVE SCALING; DESIGN OPTIMIZATION; MANUFACTURING PROCESS; NEW PRODUCT DEVELOPMENT; PROCESS DEVELOPMENT; SEMICONDUCTOR MANUFACTURING; SEMICONDUCTOR TECHNOLOGY; SPATIAL DATABASE;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0005080648     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2000.902597     Document Type: Conference Paper

References (4)

1. G.Moore, Proc. IEDM, Dec.1975, p. 11.
2. S. Davidmann, "Speaking the Language of Reuse," Electronic News, Vol. 46 (20), p. 38, May 2000.
3. EDN IP/SOC/Reuse: EDN Magazine, Special Issue, June 2000.
4. A.Balasinski, "Scheme for evaluating costs and/or benefits of manufacturing technologies," patent pending.