Efficient full-chip yield analysis methodology for OPC-corrected VLSI designs

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 461-467

  Axelrad, V ^a   Cobb, N ^b   O'Brien, M ^b   Boksha, V ^c   Do, T ^b   Donnelly, T ^b   Granik, Y ^b   Sahouria, E ^b   Balasinski, A ^d  

^a SEQUOIA Design Systems   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE; INTEGRATED CIRCUIT DESIGN; LOGIC DEVICES; PHOTOLITHOGRAPHY;

DRIVE CURRENTS; GENERAL METHODOLOGIES; LITHOGRAPHIC PATTERNS; OPTICAL PROXIMITY CORRECTIONS; PATTERN FIDELITY; PATTERN REPRODUCTION; TRANSISTOR MODEL; VLSI MANUFACTURING;

DESIGN;

EID: 0002587661     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838922     Document Type: Conference Paper

References (5)

1. C. H. Stapper, F. M. Armstrong, and K. Saji, "Integrated Circuit Yield Statistics", Proc. IEEE 71(4), April 1983
2. W. Maly, A. J. Strojwas, and S. W. Director, "VLSI Yield Prediction and Estimation: a Unified Framework", IEEE Trans. CAD, CAD-5(1), pp. 114-130 (1986)
3. C. Mack, "Yield Modeling for Photolithography", Proc. of the Interface' 94 Conf., pp. 171-182, (1994)
4. F. M. Schellenberg, V. Boksha, N. Cobb, J. C. Lai, C. H. Chen, C. Mack, "Impact of Mask Errors on Full Chip Error Budgets", SPIE Microlithography, March 1999
5. SEQUOIA Device Designer User's Manual, SEQUOIA Design Systems, 1999