A 2.05 um2 full CMOS ultra-low power SRAM cell with 0.15um generation single gate CMOS technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 579-582

  Jang, J H ^a   Kim, H S ^a   Baek, H C ^a   Na, J J ^a   Lee, K H ^a   Seo, D S ^a   Kim, K J ^a   Kim, K T ^a   Shin, Y S ^a   Hwang, C G ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; LEAKAGE CURRENTS; OPTIMIZATION; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; STATIC RANDOM ACCESS STORAGE;

PHOTO-RESIST (PR) REFLOW;

CMOS INTEGRATED CIRCUITS;

EID: 0034446645     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)