Lifetime-sensitive modulo scheduling in a production environment

IEEE Transactions on Computers

Volumn 50, Issue 3, 2001, Pages 234-249

  Llosa, Josep ^b   Ayguadé, Eduard ^b   Gonzalez, Antonio ^a,b   Valero, Mateo ^a,b   Eckhardt, Jason ^c  

^a IEEE   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c Rice University   (United States)

Author keywords

Fine grain parallelism; Instruction scheduling; Loop scheduling; Register requirements; Software pipelining; Superscalar architectures; VLIW

Indexed keywords

FINE GRAIN PARALLELISM; INSTRUCTION SCHEDULING; LOOP SCHEDULING; REGISTER REQUIREMENTS; SOFTWARE PIPELINING; SUPERSCALAR ARCHITECTURES;

ALGORITHMS; COMPUTER ARCHITECTURE; HEURISTIC METHODS; INDUSTRIAL APPLICATIONS; MULTIMEDIA SYSTEMS;

SCHEDULING;

EID: 0035272441     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.910814     Document Type: Article

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