Improved spill code generation for software pipelined loops

Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Volumn , Issue , 2000, Pages 134-144

  Zalamea, J ^a   Llosa, J ^a   Ayguade E ^a   Valero, M ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Instruction level parallelism; Register allocation; Software pipelining; Spill code

Indexed keywords

CODES (SYMBOLS); COMPUTER OPERATING PROCEDURES; HEURISTIC METHODS; ITERATIVE METHODS; PARALLEL PROCESSING SYSTEMS; SHIFT REGISTERS; STORAGE ALLOCATION (COMPUTER);

INSTRUCTION-LEVEL PARALLELISM; LOOP SCHEDULING TECHNIQUE; MEMORY TRAFFIC; PERFECT CLUB BENCHMARK; REGISTER ALLOCATION; SOFTWARE PIPELINING TECHNIQUE;

PROGRAM COMPILERS;

EID: 0034450122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/349299.349319     Document Type: Conference Paper

References (29)

1. A realistic resource-constrained software pipelining algorithm
2. Software pipelining
3. Conversion of control dependence to data dependence
4. Ictineo: A tool for instruction level parallelism research
5. Spill code minimization techniques for optimizing compilers
6. The perfect club benchmarks: Effective performance evaluation of supercomputers
7. Coloring heuristics for register allocation
8. Improvements to graph coloring register allocation
9. Register allocation via hierarchical graph coloring
10. Register allocation and spilling via graph coloring
11. An approach to scientific array processing: The architectural design of the AP120B/FPS-164 family
12. Overlapped loop support in the Cydra 5
13. Compiling for the Cydra 5
14. Stage scheduling: A technique to reduce the register requirements of a modulo schedule
15. The meeting graph: A new model for loop cyclic register allocation
16. Register allocation using cyclic interval graphs: A new approach to an old problem
17. Lifetime-sensitive modulo scheduling
18. Circular scheduling: A new technique to perform software pipelining
19. Heuristics for register-constrained software pipelining
20. Quantitative evaluation of register pressure on software pipelined loops
21. Hypernode reduction modulo scheduling
22. Register requirements of pipelined processors
23. Software pipelining in PA-RISC compilers
24. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
25. Register allocation for software pipelined loops
26. Iterative modulo scheduling: An algorithm for software pipelining loops
27. Software pipelining showdown: Optimal vs. heuristic methods in a production compiler
28. Software pipelining with register allocation and spilling