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Volumn , Issue , 1998, Pages 194-198

Register-sensitive software pipelining

Author keywords

[No Author keywords available]

Indexed keywords

HEURISTIC METHODS; ITERATIVE METHODS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); SOFTWARE ENGINEERING;

EID: 0031700692     PISSN: 10637133     EISSN: None     Source Type: None    
DOI: 10.1109/IPPS.1998.669910     Document Type: Conference Paper
Times cited : (15)

References (12)
  • 1
    • 0004072686 scopus 로고
    • Compilers — Principles, Techniques, and Tools
    • Addison-Wesley Publishing Co. MA, Reading
    • A. V. Aho R. Sethi J. D. Ullman Compilers — Principles, Techniques, and Tools 1988 Addison-Wesley Publishing Co. MA, Reading
    • (1988)
    • Aho, A.V.1    Sethi, R.2    Ullman, J.D.3
  • 2
    • 85044971726 scopus 로고    scopus 로고
    • Dani Software Pipelining for VLIW Architectures
    • India, Bangalore
    • K Amod Dani Software Pipelining for VLIW Architectures Jan. 1997 India, Bangalore Dept. of Computer Science and Automation, Indian Institute of Science
    • (1997)
    • Amod, K1
  • 4
    • 0029487619 scopus 로고
    • Stage scheduling: A technique to reduce the register requirements of a modulo schedule
    • MI
    • A. E. Eichenberger E. S. Davidson Stage scheduling: A technique to reduce the register requirements of a modulo schedule Proc. of the 28th Ann. Intl. Symp. on Microarchitecture 338 349 Proc. of the 28th Ann. Intl. Symp. on Microarchitecture Ann Arbor MI 1995-Dec.
    • (1995) , pp. 338-349
    • Eichenberger, A.E.1    Davidson, E.S.2
  • 5
    • 0028768024 scopus 로고
    • Minimum register requirements for a modulo schedule
    • CA
    • A. E. Eichenberger E. S. Davidson S. G. Abraham Minimum register requirements for a modulo schedule Proc. of the 27th Ann. Intl. Symp. on Microarchitecture 75 84 Proc. of the 27th Ann. Intl. Symp. on Microarchitecture San Jose CA 1994-Dec.
    • (1994) , pp. 75-84
    • Eichenberger, A.E.1    Davidson, E.S.2    Abraham, S.G.3
  • 6
    • 0028768026 scopus 로고
    • Minimizing register requirements under resource-constrained rate-optimal software pipelining
    • CA
    • R. Govindarajan E. R. Altman G. R. Gao Minimizing register requirements under resource-constrained rate-optimal software pipelining Proc. of the 27th Ann. Intl. Symp. on Microarchitecture 85 94 Proc. of the 27th Ann. Intl. Symp. on Microarchitecture San Jose CA 1994-Dec.
    • (1994) , pp. 85-94
    • Govindarajan, R.1    Altman, E.R.2    Gao, G.R.3
  • 8
    • 0027870809 scopus 로고
    • Lifetime-sensitive modulo scheduling
    • NM
    • R. A. Huff Lifetime-sensitive modulo scheduling Proc. of the ACM SIGPLAN '93 Conf. on Programming Language Design and Implementation 258 267 Proc. of the ACM SIGPLAN '93 Conf. on Programming Language Design and Implementation Albuquerque NM 1993-June-23-25
    • (1993) , pp. 258-267
    • Huff, R.A.1
  • 9
    • 0042650298 scopus 로고
    • Software pipelining: An effective scheduling technique for VLIW machines
    • GA
    • M. Lam Software pipelining: An effective scheduling technique for VLIW machines Proc. of the SIGPLAN '88 Conf. on Programming Language Design and Implementation 318 328 Proc. of the SIGPLAN '88 Conf. on Programming Language Design and Implementation Atlanta GA 1988-June
    • (1988) , pp. 318-328
    • Lam, M.1
  • 10
    • 0029488251 scopus 로고
    • Hypernode reduction modulo scheduling
    • MI
    • J. Llosa M. Valero E. Ayguadé A. González Hypernode reduction modulo scheduling Proc. of the 28th Ann. Intl. Symp. on Microarchitecture 350 360 Proc. of the 28th Ann. Intl. Symp. on Microarchitecture Ann Arbor MI 1995-Dec.
    • (1995) , pp. 350-360
    • Llosa, J.1    Valero, M.2    Ayguadé, E.3    González, A.4
  • 11
    • 0002017307 scopus 로고
    • Instruction-level parallel processing: History, overview and perspective
    • B. R. Rau J. A. Fisher Instruction-level parallel processing: History, overview and perspective Jl. of Supercomputing 7 9 50 May 1993
    • (1993) Jl. of Supercomputing , vol.7 , pp. 9-50
    • Rau, B.R.1    Fisher, J.A.2
  • 12
    • 0028768013 scopus 로고
    • Iterative modulo scheduling: An algorithm for software pipelining loops
    • CA
    • B. R. Rau Iterative modulo scheduling: An algorithm for software pipelining loops Proc. of the 27th. Ann. Intl. Symp. on Microarchitecture 63 74 Proc. of the 27th. Ann. Intl. Symp. on Microarchitecture San Jose CA 1994-Dec.
    • (1994) , pp. 63-74
    • Rau, B.R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.