Behavioral fault modeling in a VHDL synthesis environment

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 333-340

  Hayne, Ronald J ^a   Johnson, Barry W ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMBINATORIAL CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DIGITAL ARITHMETIC; HIGH LEVEL LANGUAGES; LOGIC DESIGN;

ARITHMETIC LOGIC UNIT; BEHAVIORAL FAULT MODELING; SINGLE STUCK LINE FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0032646008     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (16)