Identification of primitive faults in combinational and sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 12, 2001, Pages 1426-1442

  Tekumalla, Ramesh C ^a,b   Menon, Premachandran R ^a,c  

^a IEEE   (United States)

^b Sun Microsystems ^*  (United States)

^c University of Massachusetts   (United States)

Author keywords

Delay faults; Primitive faults; Test generation; Timing verification

Indexed keywords

DELAY FAULTS; NONSCAN SEQUENTIAL CIRCUITS;

COMBINATORIAL CIRCUITS; ELECTRIC FAULT LOCATION; FLIP FLOP CIRCUITS; FORMAL LOGIC; IDENTIFICATION (CONTROL SYSTEMS); VECTORS;

SEQUENTIAL CIRCUITS;

EID: 0035673745     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.969436     Document Type: Article

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