Primitive path delay faults: identification and their use in timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 11, 2000, Pages 1347-1362

  Sivaraman, Mukund ^b   Strojwas, Andrzej J ^a,c  

^a IEEE

^b HEWLETT PACKARD COMPANY   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL METHODS; ELECTROMAGNETIC WAVE PROPAGATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; SHORT CIRCUIT CURRENTS; THEOREM PROVING; TIMING CIRCUITS;

DELAY FAULT TESTING; MULTILEVEL LOGIC CIRCUIT; PATH DELAY FAULTS; SIGNAL INTERACTION EFFECTS; SIGNAL PROPAGATION; TIMING ANALYSIS;

DELAY CIRCUITS;

EID: 0034313572     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.892858     Document Type: Article

References (38)