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Volumn , Issue , 1997, Pages 636-641
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Test generation for primitive path delay faults in combinational circuits
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Author keywords
[No Author keywords available]
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Indexed keywords
INTEGRATED CIRCUIT TESTING;
MATHEMATICAL MODELS;
PRIMITIVE PATH DELAY FAULTS;
COMBINATORIAL CIRCUITS;
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EID: 0031378507
PISSN: 10923152
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/iccad.1997.643605 Document Type: Conference Paper |
Times cited : (12)
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References (18)
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