Improving the RF performance of 0.18 μm CMOS with deep n-well implantation

IEEE Electron Device Letters

Volumn 22, Issue 10, 2001, Pages 481-483

  Su, Jiong Guang ^b   Hsu, Heng Ming ^c   Wong, Shyh Chyi ^a,c   Chang, Chun Yen ^a,b   Huang, Tiao Yuan ^a,b,d   Sun, Jack Yuan Chen ^a,c  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^d NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

CMOS; Deep n well; Maximum oscillation frequency; Radio frequency; Unity current gain cutoff frequency

Indexed keywords

WELL IMPLANTATION;

CAPACITANCE; ELECTRIC IMPEDANCE; MOSFET DEVICES; SILICON WAFERS; SUBSTRATES;

CMOS INTEGRATED CIRCUITS;

EID: 0035473961     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.954918     Document Type: Article

References (14)

1. Well-controlled selectively under-etched Si/SiGe gates for RF and high performance CMOS
2. High performance scaled down Si LDMOSFET with thin gate bird's beak technology for RF power amplifier
3. Microwave performance of optically fabricated T-gate thin film silicon-on-sapphire based MOSFET's
4. High performance RF characteristics of raised gate/source/drain CMOS with Co salicide
5. An epitaxial channel MOSFET for improving flicker noise under low supply voltage
6. th epitaxial-channel MOSFET's
7. Signal isolation in BiCMOS mixed mode integrated circuits
8. An improved de-embedding technique for on-wafer high-frequency characterization
9. Accurate modelling and parameter extraction for MOS transistors valid up to 10 GHz
10. CMOS RF modelling for GHz communication IC's
11. Analysis of floating substrate effects on the intrinsic gate capacitance of SOI MOSFET's using two-dimensional device simulation
12. Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications
13. New insights on RF CMOS stability related to bias, scaling and temperature