Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 154-155

  Maeda, S ^a   Wada, Y ^a   Yamamoto, K ^a   Komurasaki, H ^a   Matsumoto, T ^a   Hirano, Y ^a   Iwamatsu, T ^a   Yamaguchi, Y ^a   Ipposhi, T ^a   Ueda, K ^a   Mashiko, K ^a   Maegawa, S ^a   Inuishi, M ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY OF SOLIDS; LOGIC CIRCUITS; LSI CIRCUITS; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

HIGH RESISTIVITY SUBSTRATES (HRS); HYBRID TRENCH ISOLATION;

CMOS INTEGRATED CIRCUITS;

EID: 0033682238     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)