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Volumn 46, Issue 7, 1999, Pages 1378-1383

An 0.18-μm CMOS for mixed digital and analog applications with zero-Volt-Vth epitaxial-channel MOSFET's

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; DIGITAL INTEGRATED CIRCUITS; EPITAXIAL GROWTH; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0032671606     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.772479     Document Type: Article
Times cited : (14)

References (17)
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  • 7
    • 0028754967 scopus 로고
    • Application of semiclassical device simulation to trade-off studies for sub-0.1-μm MOSFET's
    • C. Fiegna, H. Iwai, T. Wada, T. Saito, and E. Sangiorgi, "Application of semiclassical device simulation to trade-off studies for sub-0.1-μm MOSFET's," in IEDM Tech. Dig., 1994, pp. 437-450.
    • (1994) IEDM Tech. Dig. , pp. 437-450
    • Fiegna, C.1    Iwai, H.2    Wada, T.3    Saito, T.4    Sangiorgi, E.5
  • 10
    • 0028756728 scopus 로고
    • Design methodology for low-voltage MOSFET's
    • T. Andoh, A. Furukawa, and T. Kunio, "Design methodology for low-voltage MOSFET's," in IEDM Tech. Dig., 1994, pp. 79-82.
    • (1994) IEDM Tech. Dig. , pp. 79-82
    • Andoh, T.1    Furukawa, A.2    Kunio, T.3
  • 11
    • 0029544307 scopus 로고
    • A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 μm n-n gate CMOS technology
    • H. Abiko, A. Ono, R. Ueno, S. Masuoka, S. Shishiguchi, K. Nakajima, and I.Sakai, "A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 μm n-n gate CMOS technology," in Symp. VLSI Tech. Dig., 1995, pp. 23-24.
    • (1995) Symp. VLSI Tech. Dig. , pp. 23-24
    • Abiko, H.1    Ono, A.2    Ueno, R.3    Masuoka, S.4    Shishiguchi, S.5    Nakajima, K.6    Sakai, I.7
  • 12
    • 0029707035 scopus 로고    scopus 로고
    • High-performance double-layer epitaxial-channel P-MOSFET compatible with a single gate CMOSFET
    • H. Matsuhashi, T. Ochiai, M. Kasai, T. Nakamura, and S. Nishikawa, "High-performance double-layer epitaxial-channel P-MOSFET compatible with a single gate CMOSFET," in Symp. on VLSI Tech. Dig., 1996, pp. 36-37.
    • (1996) Symp. on VLSI Tech. Dig. , pp. 36-37
    • Matsuhashi, H.1    Ochiai, T.2    Kasai, M.3    Nakamura, T.4    Nishikawa, S.5
  • 13
    • 0023995279 scopus 로고
    • Deep-submicrometer MOS device fabrication using a photoresist-ashing technique
    • J. Chung, M. C.Jeng, J. E. Moon, A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, "Deep-submicrometer MOS device fabrication using a photoresist-ashing technique," in IEEE Electron Device Lett., vol. EDL-9, pp. 186-188, 1988.
    • (1988) IEEE Electron Device Lett. , vol.EDL-9 , pp. 186-188
    • Chung, J.1    Jeng, M.C.2    Moon, J.E.3    Wu, A.T.4    Chan, T.Y.5    Ko, P.K.6    Hu, C.7
  • 14
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    • Sub-50 nm gate length n-MOSFET's with 10 nm phosphorus source and drain junctions
    • M. Ono, M. Saito, T. Yoshitomi, C. Firgna, T. Ohguro, and H. Iwai, "Sub-50 nm gate length n-MOSFET's with 10 nm phosphorus source and drain junctions," in IEDM Tech. Dig., 1993, pp. 119-122.
    • (1993) IEDM Tech. Dig. , pp. 119-122
    • Ono, M.1    Saito, M.2    Yoshitomi, T.3    Firgna, C.4    Ohguro, T.5    Iwai, H.6
  • 16
    • 0009054973 scopus 로고
    • Scanning tunneling microscopy observation of hydrogen-terminated Si(111) surfaces at room temperature
    • K. Usuda, H. Kanaya, and K. Yamada, "Scanning tunneling microscopy observation of hydrogen-terminated Si(111) surfaces at room temperature," in Appl. Phys. Lett., vol. 64, pp. 3240-3242, 1994.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.