Synthesis of a new manufacturable high-quality graded gate oxide for Sub-0.2 μm technologies

IEEE Transactions on Electron Devices

Volumn 48, Issue 9, 2001, Pages 2016-2021

  Roy, Pradip Kumar ^a,b   Chen, Yuanning ^a,b   Chetlur, Sundar ^b  

^a IEEE   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

Bias temperature; CMOS manufacturability; Fast ramp furnace; Gate oxide; Gate oxide reliability; Hot carrier aging; SiO 2 interface; V t stability; Viscoelastic transition in SiO 2

Indexed keywords

BIAS TEMPERATURE; CMOS MANUFACTURABILITY; FAST RAMP FURNACE; GATE OXIDE RELIABILITY; HOT CARRIER AGING; VISCOELASTIC TRANSITION;

AGING OF MATERIALS; HOT CARRIERS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (MATERIALS); OXIDES; RELIABILITY; SEMICONDUCTOR GROWTH; STRESS RELAXATION; SYNTHESIS (CHEMICAL); TEMPERATURE; VISCOELASTICITY;

CMOS INTEGRATED CIRCUITS;

EID: 0035444699     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.944191     Document Type: Article

References (24)

1. Scaling the gate dielectric
2. MOS scaling: Transistor challenges for the 21st century
3. Stacked high-ε gate dielectric for gigascale integration in metal-oxide-semiconductor technologies
4. Reliability projection for ultra-thin oxides at low voltage
5. 2 during growth
6. 2 system properties
7. Synthesis and characterization of high quality ultrathin gate oxides for VLSI/ULSI circuits
8. Semiconductor device low degree density oxide
9. Thermal processes: Evolution of fast-ramp funaces
10. A merged 2.5 V and 3.3 V 0.25 um CMOS technology
11. Synthesis of high-quality ultra-thin gate oxides for ULSI applications
12. 2 interface using TEM lattice imaging and X-ray microdiffraction technique
13. Introduction to passive data collection
14. Thermal processing options
15. Gate dielectrics
16. 2/Si interface on sub 4 nm-thick gate oxide reliability
17. 2 interface
18. Reliability of ultra-thin gate oxide below 3 nm in the direct tunneling regime
19. Time dependent dielectric degradation (TDDB) influenced by ultrathin film oxidation process
20. 2 films
21. Hot electron effects in MOSFET's
22. Analysis of mechanism for hot carrier induced VLSI circuit degradation
23. Bias temperature degradation of PMOSFETs: Mechanism and suppression
24. + poly Si gate P-MOSFETs