Power consumption of hybrid circuits of single-electron transistors and complementary metal-oxide-semiconductor field-effect transistors

IEICE Transactions on Electronics

Volumn E84-C, Issue 8, 2001, Pages 1066-1070

  Uchida, Ken ^a   Koga, Junji ^a   Oha, Ryuji ^a   Toriumi, Akira ^a,b  

^a TOSHIBA CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

MOSFET; Power; Single electron; Tunneling

Indexed keywords

AMPLIFIERS (ELECTRONIC); CALCULATIONS; CAPACITANCE; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRON TUNNELING; LOGIC CIRCUITS; MOSFET DEVICES;

CMOS AMPLIFIERS; HYBRID LOGIC CIRCUITS; INTERCONNECT CAPACITANCE; POWER CONSUMPTION; SINGLE ELECTRON TRANSISTOR LOGIC TREES; SINGLE ELECTRON TRANSISTORS;

TRANSISTORS;

EID: 0035422444     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. Coulomb blockade effects in edge quantum wire SOI-MOSFETs
2. Coulomb blockade effects in edge quantum wire SOI MOSFETs
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5. Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits
6. Influence of quantum confinement effects on single electron and single hole transistors
7. Planar non-volatile memory with single-electron channel fabricated on a hyper-thin SOI film
8. Fabrication method for IC-oriented Si single-electron transistors
9. Complementary digital logic based on the Coulomb blockade