Fully depleted 20-nm SOI CMOSFETs with W - Clad gate/source/drain layers

IEEE Transactions on Electron Devices

Volumn 48, Issue 7, 2001, Pages 1380-

  Takahashi, Mitsutoshi ^b   Ohno, Terukazu ^a,b   Sakakibara, Yutaka ^c   Takayama, Kazuhiko ^b  

^a IEEE

^b NTT CORPORATION   (Japan)

^c NTT Advance Technology Corporation   (Japan)

Author keywords

Complementary metal oxide semiconductor field effect transistors (CMOSFETs); Contacts; Fully depleted; Separation by implanted oxygen (SIMOX); Silicon on insulator technology

Indexed keywords

FABRICATION; GATES (TRANSISTOR); SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; ULTRATHIN FILMS;

ULTRATHIN DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 0035396864     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.930655     Document Type: Article

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