A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 7, 2001, Pages 1120-1126

  Fujisawa, Hiroki ^a,b   Takahashi, Tsugio ^a,b   Nakamura, Masayuki ^b   Kajigaya, Kazuhiko ^b  

^a IEEE   (Japan)

^b Elpida Memory Inc   (Japan)

Author keywords

Data amplifier; DRAM chips; High speed; Low power

Indexed keywords

DIFFERENTIAL DATA TRANSFER; DUAL-PHASE CLOCK; DYNAMIC LATCHED AMPLIFIER; SYNCHRONOUS DYNAMIC RANDOM ACCESS STORAGE;

DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT MANUFACTURE; PHASE CONTROL; TIMING CIRCUITS;

AMPLIFIERS (ELECTRONIC);

EID: 0035390928     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.933470     Document Type: Article

References (10)

1. 2 16-bank 1-Gb DDR SDRAM with hybrid bitline architecture
2. A 250-Mb/s/pin 1-Gb double-data-rate SDRAM with a bi-directional delay and an interbank shared redundancy scheme
3. An experimental 220-Mhz 1-Gb DRAM with a distributed-column-control architecture
4. A 2.5-V 333-Mb/s/pin 1-Gbit double-data-rate synchronous DRAM
5. 500-Mb/s nonprecharged data bus for high-speed DRAMs
6. A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture
7. A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme
8. A circuit technology for high-speed battery-operated 16-Mb CMOS DRAMs
9. A dual-phase-controlled dynamic latched (DDL) amplifier for high-speed and low-power DRAMs
10. Circuit techniques for multibit parallel testing of 64 Mb DRAMs and beyond