A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 9, 1996, Pages 1285-1294

  Yamauchi, Hiroyuki ^a,b,c,d,e   Matsuzawa, Akira ^a,b,d,f,g,h  

^a IEEE

^b PANASONIC CORPORATION   (Japan)

^c TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

^d Semiconductor Research Center

^e TOHOKU UNIVERSITY

^f TOHOKU UNIVERSITY   (Japan)

^g Matsushita Elec Indust Co Ltd ^*

^h IEICE

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTIC VARIABLES CONTROL; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DETECTOR CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY EFFICIENCY; INTERFERENCE SUPPRESSION; MULTIPLEXING; POWER CONTROL;

CHARGE RECYCLING BUS (CRB); DATA TRANSITION DETECTOR (DTD) CIRCUIT; POWER REDUCTION; SIGNAL SWING SUPPRESSING STRATEGY; SINGLE SIGNAL LINE (SSL); TIME MULTIPLEXED DIFFERENTIAL DATA TRANSFER (TMD) SCHEME;

COMPUTER ARCHITECTURE;

EID: 0030241263     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.535412     Document Type: Article

References (5)

1. H. Yamauchi et al., "A low power complete charge-recycling bus architecture for ultra-high data rate ULSI's," in Symp. VLSI Circ. Dig. Tech. Papers, June 1994, pp. 21-22.
2. A. Chandrakasan et al., "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4SC, pp. 473-484, Apr. 1992.
3. H. Yamauchi et al., "A 20 ns battery-operated 16 Mb CMOS DRAM," ISSCC Dig. Tech. Papers, pp. 44-45, Feb. 1993.
4. _, "A low power signal-swing suppressing strategy using time-multiplexed differential data-transfer (TMD) scheme," in Symp. Low Power Electr. Dig. Tech. Papers, Session no. 6.2, Oct. 1995, pp. 48-49.
5. T. Yoshihara et al., "A twisted bit line technique for multi-Mb DRAM's," in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 238-239.