A dual-phase-controlled dynamic latched (DDL) amplifier for high-speed and low-power DRAMs

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 184-187

  Fujisawa, Hiroki ^a   Takahashi, T ^a   Nakamura, M ^a   Kajigaya, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA PENALTY; CIRCUIT TECHNOLOGY; CONTROL TECHNIQUES; DEVICE FLUCTUATION; DIFFERENTIAL DATA; OPERATING CURRENTS; OPERATING MARGINS; TRANSFER SCHEME;

DATA TRANSFER;

CLOCKS;

EID: 79960869176     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. H. Yoon, et al., "A 2.5-V, 333-Mb/s/pin, 1-Gbit, Double-Data-Rate Synchronous DRAM," IEEE J. Solid-State Circ., vol. 34, no. 11, pp. 1589-1598, Nov. 1999.
2. M. Saito, et al., "500-Mb/s Nonprecharged Data Bus for High-Speed DRAM's," IEEE J. Solid-State Circ., vol. 33, no. 11, pp. 1720-1729, Nov. 1998.
3. M. Taguchi, et al., "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture," IEEE J. Solid-State Circ., vol. 26, no. 11, pp. 1493-1497, Nov. 1991.
4. H. Yamauchi, et al., "A Signal-Swing Suppressing Strategy for Power and Layout Area Savings Using Time-Multiplexed Differential Data-Transfer Scheme," IEEE J. Solid-State Circ., vol. 31, no. 9, pp. 1285-1294, Sep. 1996.
5. T. Sakuta, et al., "Circuit Techniques for Multi-Bit Parallel Testing of 64Mb DRAMs and Beyond," in Sym. on VLSI Circ. Dig. Tech. Papers, 1992, pp.60-61.