390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1580-1588

  Kirihata, Toshiaki ^a   Mueller, Gerhard ^a,b   Ji, Brian ^a,c   Frankowsky, Gerd ^a,d   Ross, John M ^a   Terletzki, Hartmud ^a   Netis, Dmitry G ^a   Weinfurtner, Oliver ^a   Hanson, David R ^a   Daniel, Gabriel ^a   Hsu, Louis Lu Chen ^a   Storaska, Daniel W ^a   Reith, Armin M ^a   Hug, Marco A ^a   Guay, Kevin P ^a   Selz, Manfred ^a   Poechmueller, Peter ^a   Hoenigschmid, Heinz ^a   Wordeman, Matthew R ^a  

^a IBM   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c IBM MICROELECTRONICS   (United States)

^d INFINEON TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER ARCHITECTURE; DECODING; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; SEMICONDUCTOR DEVICE MANUFACTURE;

CELLS/LOCAL-BITLINES (LBL); DOUBLE-DATA-RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DDR SDRAM); HIERARCHICAL COLUMN-SELECT-LINES (CSL); HYBRID BITLINE ARCHITECTURE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 18544411374     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799866     Document Type: Article

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