500-Mb/s nonprecharged data bus for high-speed DRAM's

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1720-1729

  Saito, Miyoshi ^a,b,c,d   Ogawa, Junji ^a,b,e   Tamura, Hirotaka ^a,e,f   Wakayama, Shigetoshi ^a,g   Araki, Hisakatsu ^a,e,h   Cheung, Tsz Shing ^a   Gotoh, Kohtaroh ^a   Aikawa, Tadao ^a   Suzuki, Takaaki ^a   Taguchi, Masao ^a   Imamura, Takeshi ^a,b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b IEEE   (United States)

^c TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^d AMERICAN PHYSICAL SOCIETY   (United States)

^e UNIVERSITY OF TOKYO   (Japan)

^f JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^g OSAKA UNIVERSITY   (Japan)

^h TOKYO UNIVERSITY OF SCIENCE   (Japan)

Author keywords

Data rate; Data bus amplifier; Differential partial response detection; High speed DRAM's; Intersymbol interference; Isolated sense amplifier; Nonprecharged data bus; Partial response detection

Indexed keywords

AMPLIFIERS (ELECTRONIC); INTERFERENCE SUPPRESSION; INTERSYMBOL INTERFERENCE;

DIFFERENTIAL PARTIAL-RESPONSE DETECTION; ISOLATED SENSE AMPLIFIERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032202809     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726566     Document Type: Article

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