2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1589-1599

  Yoon, Hongil ^a   Cha, Gi Won ^a   Yoo, Changsik ^b   Kim, Nam Jong ^a   Kim, Keum Yong ^a   Lee, Chang Ho ^a   Lim, Kyu Nam ^a   Lee, Kyuchan ^a   Jeon, Jun Young ^a   Jung, Tae Sung ^a   Jeong, Hongsik ^a   Chung, Tae Young ^a   Kim, Kinam ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

^b ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRONICS PACKAGING; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

DELAY-LOCKED LOOPS (DLL); DOUBLE-DATA-RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DDR SDRAM); PHASE DETECTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033221599     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799867     Document Type: Article

References (9)

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