CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 6, 2001, Pages 924-932

  González, Alejandro F ^a,b   Bhattacharya, Mayukh ^b   Kulkarni, Shriram ^b   Mazumder, Pinaki ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

CMOS; Multiple valued logic; Negative differential resistance; Negative resistance; Quantum electronics; Resonant tunneling diode; RTD

Indexed keywords

MULTIPLE VALUED LOGIC; NEGATIVE DIFFERENTIAL RESISTANCE; RESONANT TUNNELING DIODE;

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; LOGIC CIRCUITS; MOSFET DEVICES; QUANTUM ELECTRONICS; TUNNEL DIODES;

CMOS INTEGRATED CIRCUITS;

EID: 0035363921     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924855     Document Type: Article

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