Development of a run-time reconfiguration system with low reconfiguration overhead

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 28, Issue 1-2, 2001, Pages 97-113

  Heron, J P ^a   Woods, R ^a   Sezer, S ^a   Turner, R H ^a  

^a Integrated Silicon Systems Ltd   (United Kingdom)

Author keywords

Dynamic reconfiguration; FIR filtering; FPGA implementation; High speed arithmetic; Reconfiguration framework

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER HARDWARE; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; FIR FILTERS; MICROCONTROLLERS;

RUN-TIME RECONFIGURABLE (RTR) SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035341715     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008115306599     Document Type: Article

References (27)

1. A guide to using Field Programmable Gate Arrays (FPGAs) for application-specific digital signal processing performance
2. Design methodologies for partially reconfigured systems
3. Applying an XC6200 to real-time image processing
4. Advances in adaptive signal processing: Totally adaptive systems
5. The design and implementation of a context switching FPGA
6. An FPGA-based coprocessor for ATM firewalls
7. Automating production of run-time Reconfigurable designs
8. Configuration compression for the Xilinx XC6200 FPGA
9. Design methodologies for partially reconfigured systems
10. Configurable computing
11. A dynamic reconfiguration run-time system
12. A framework for developing parameterised FPGA libraries
13. Improving functional density using run-time circuit reconfiguration
14. A virtual hardware operating system for the Xilinx XC6200
15. A constant coefficient multiplier for the XC6200
16. Pipeline morphing and virtual pipelines
17. Automated target recognition on splash 2
18. The swappable logic unit: A paradigm for virtual hardware
19. Compilation tools for run-time reconfigurable designs
20. A Run-Time Reconfigurable engine for image interpolation
21. Fast partial reconfiguration for FCCMs
22. Architectural strategies for implementing an image processing algorithm on XC6200 FPGA
23. A VLSI module for high performance multiplication, division and square root