Applying an XC6200 to real-time image processing

IEEE Design and Test of Computers

Volumn 15, Issue 1, 1998, Pages 30-38

  Woods, Roger ^a,b,c   Trainor, David ^a,c,d   Heron, Jean Paul ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b IEEE   (United Kingdom)

^c IEEE ^*  (United Kingdom)

^d Integrated Silicon Systems   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL TRANSFORMATIONS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

DISCRETE COSINE TRANSFORM (DCT); FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES;

EID: 0031680156     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.655180     Document Type: Article

References (11)

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