Architectural strategies for implementing an image processing algorithm on XC6000 FPGA

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1142, Issue , 1996, Pages 317-326

  Heron, J P ^a   Woods, R F ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM COMPILERS;

CUSTOM COMPUTING; FPGA TECHNOLOGY; HIGH-LEVEL DESIGN; IMAGE PROCESSING ALGORITHM; LAPLACIANS;

IMAGE PROCESSING;

EID: 84955604341     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61730-2_34     Document Type: Conference Paper

References (6)

1. W. Luk, D. Ferguson, I. Page, "Structured Hardware Compilation of Parallel Programs", More FPGA's, Abingdon EE&CS Books 1993, pp 213.
2. N. B. Bhat, "A New Library-Based Mapper for LUT FPGA's", More FPGA's, Abingdon EE&CS Books 1993, pp 138.
3. R. Woods, D. Crookes, W. Cochrane, A. Mitchell "Image Co-Processor Based on Reconfigurable Hardware", Irish DSP and Control Colloquium, July 7-8th, 1994, pp 341-350
4. XC6200 FPGA Family Data Sheet, Xilinx Inc. 1996
5. M. Alexander, J. Cohoon, J. Ganley, G. Robins "Performance-Oriented Placement and Routing For Field-Programmable Gate Arrays" Euro-DAC. '95 Proceedings. IEEE Computer Society Press, pp 80.
6. D. W. Trainor, R. F. Woods, J. V. McCanny, "Architectural Synthesis of an Image Processing Algorithm Using Iris", Proceedings of the IEEE Workshop on VLSI Signal Processing, Osaka, Japan, Oct. 16-18 1995, pp. 167-176.