Interconnect scaling scenario using a chip level interconnect model

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 53-54

  Yamashita, Kyoji ^a   Odanaka, Shinji ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; METALLIC SUPERLATTICES; MICROELECTRONICS; SEMICONDUCTOR DEVICE MODELS;

INTERCONNECT SCALING;

VLSI CIRCUITS;

EID: 0030708102     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.1997.623691     Document Type: Conference Paper

References (7)