Multiobjective optimization of VLSI interconnect parameters

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 12, 1998, Pages 1252-1261

  Anand, M B ^a   Shibata, Hideki ^a   Kakumu, Masakazu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Integrated circuit design; Integrated circuit interconnections; Integrated circuit modeling; Optimization methods

Indexed keywords

EID: 0000965393     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.736565     Document Type: Article

References (17)

1. G.A. Sai-Halasz, "Performance trends in high-end microprocessors," Proc. IEEE, vol. 83, p. 20, Jan. 1995.
2. H.B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990, pp. 429-459.
3. L.S. Lasdon, A. Waren, A. Jain, and M. Ratner, "Design and testing of a generalized reduced gradient code for nonlinear programming," ACM Trans. Math. Software, vol. 4, no. 1, p. 34, 1978.
4. W.L. Winston, Operations Research: Applications and Algorithms, 3rd ed. Belmont, CA: Duxbury, 1994.
5. W.E. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. Circuits Syst., vol. CAS-26, no. 4, p. 272, 1979.
6. J.A. Davis, V. De, and J. Meindl, "Optimal low power interconnect networks," in 1996 Symp. VLSI Tech. Dig. Tech. Papers, 1996, p. 78.
7. J.A. Davis, V. K. De, and J. D. Meindl, "A stochastic wire length distribution for gigascale integration (GSI), in Proc. 1997 Custom Integrated Circuits Conf., 1997, p. 145.
8. C.G. Hsi and S. G. Tucker, "Figures of merit for system path time estimation," in ICCD Dig., 1990, p. 49.
9. G. Baccarani, M.R. Wordeman, and R. H. Dennard, "Generalized scaling theory and its application to an 1/4 micrometer MOSFET design," IEEE Trans. Electron Devices, vol. ED-31, no. 4, p. 452, 1984.
10. J.S. Liptay, "Design of the IBM enterprise system/9000 high-end processors," IBM J. Res. Develop., vol. 36, p. 713, 1992.
11. H.B. Bakoglu and J. D. Meindl, "Optimal interconnections for VLSI," IEEE Trans. Electron Devices, vol. ED-32, no. 5, p. 903, 1985.
12. "National technology roadmap for semiconductors," SIA, San Jose, CA, 1997.
13. T. Sakurai and K. Tamaru, "Simple formulas for two- and three-dimensional capacitances," IEEE Trans. Electron Devices, vol. ED-30, no. 2, p. 183, 1983.
14. T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Circuits, vol. SC-18, no. 4, p. 418, 1983.
15. D.C. Edelstein, G. A. Sai-Halasz and Y.-J. Mii, "VLSI on-chip interconnection performance simulations and measurements," IBM J. Res. Develop., vol. 39, no. 4, p. 383, 1995.
16. J. Cong and K. Leung, "Optimal wiresizing under elmore delay model," IEEE Trans. Computer-Aided Design, vol. 14, no. 3, p. 321, 1995.
17. C.-P. Chen, Y.-P. Chen, and D.F. Wong, "Optimal wire-sizing formula under the Elmore delay model," in Proc. ACM/IEEE Design Automation Conf., 1996, p. 487.