Shared buffer implementations of signal processing systems using lifetime analysis techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 2, 2001, Pages 177-198

  Murthy, Praveen K ^a,b   Bhattacharyya, Shuvra S ^a,c  

^a IEEE   (United States)

^b Angeles Design Systems   (United States)

^c UNIVERSITY OF MARYLAND   (United States)

Author keywords

Block diagram compiler; DSP software synthesis; Dynamic programming; Dynamic storage allocation; Lifetime analysis; Loop fusion; Memory allocation; Static scheduling; Synchronous dataflow; Weighted interval graph coloring

Indexed keywords

BLOCK DIAGRAM COMPILER; DIGITAL SIGNAL PROCESSING SOFTWARE SYNTHESIS; DYNAMIC STORAGE ALLOCATION; LIFETIME ANALYSIS; LOOP FUSION; STATIC SCHEDULING; SYNCHRONOUS DATAFLOW; WEIGHTED INTERVAL GRAPH COLORING;

ALGORITHMS; BUFFER STORAGE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE SELECTION AND EVALUATION; DATA FLOW ANALYSIS; DIGITAL SIGNAL PROCESSING; DYNAMIC PROGRAMMING; GRAPH THEORY; HEURISTIC METHODS; PROGRAM COMPILERS; RESOURCE ALLOCATION; STORAGE ALLOCATION (COMPUTER);

COMPUTER AIDED LOGIC DESIGN;

EID: 0035248448     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.908427     Document Type: Article

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