Systematic consolidation of input and output buffers in synchronous dataflow specifications

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2000, Pages 673-682

  Murthy, Praveen K ^a   Bhattacharyya, Shuvra S ^b  

^a Angeles Design Systems   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTATIONAL METHODS; COMPUTER PROGRAMMING; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; GRAPH THEORY; MATHEMATICAL MODELS; MERGING; POLYNOMIALS; SOFTWARE ENGINEERING;

HYBRID ALGORITHM; POLYNOMIAL TIME ALGORITHM; SOFTWARE SYNTHESIS; SYNCHRONOUS DATAFLOW;

DATA FLOW ANALYSIS;

EID: 0034512189     PISSN: 15206130     EISSN: None     Source Type: Journal    
DOI: 10.1109/SIPS.2000.886765     Document Type: Article

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