Automating the sizing of analog CMOS circuits by consideration of structural constraints

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 323-327

  Schwencker, R ^a,b   Eckmueller, J ^b   Graeb, H ^a   Antreich, K ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CMOS CIRCUIT; ANALOG INTEGRATED CIRCUIT; SIZING PROCESS; SIZING RULES; STRUCTURAL CONSTRAINTS; TRUST-REGION METHODS;

CMOS INTEGRATED CIRCUITS; EXHIBITIONS; ITERATIVE METHODS; LINEAR INTEGRATED CIRCUITS;

ANALOG CIRCUITS;

EID: 0006916472     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761141     Document Type: Conference Paper

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