Yield-reliability modeling for fault tolerant integrated circuits

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 29-38

  Barnett, T S ^a   Singh, A D ^a   Nelson, V P ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DEFECTS; FAILURE ANALYSIS; POISSON DISTRIBUTION; PROBABILITY; RELIABILITY; YIELD STRESS;

DEFECT TOLERANT CIRCUITS; FAULT TOLERANT INTEGRATED CIRCUITS; YIELD-RELIABILITY MODELING;

INTEGRATED CIRCUIT TESTING;

EID: 0035201740     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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12. A unified negative binomial distribution for yield analysis of defect tolerant circuits
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